The present invention relates to sigma-delta (ΣΔ) analog-to-digital converters.
In conventional ΣΔ converters, a front-end stage samples an input voltage with charge storage components (i.e., storage capacitors), and the charge is then accumulated on another set of components (i.e., integrating capacitors). The integrated samples are then quantized by an analog-to-digital converter (ADC), for example, a flash ADC. The ADC output is also looped back via a feedback DAC to be subtracted from the input voltage. The feedback DAC samples a reference voltage dependent on the ADC output bit state(s).
A typical ΣΔ ADC includes: a loop filter, integrator(s), an ADC, a feedback DAC, and a subtractor. A ΣΔ ADC receives an analog input signal x[t] over time t and generate an N-valued digital output signal y[n] over discrete times ‘n’. Resolution of the output signal y[n] is be determined by the resolution of the ADC.
During operation, the subtractor subtracts from the input signal x[t] a feedback signal, labeled ya[t]. The feedback signal ya[t] is be an analog representation of the output signal y[n] of the DAC. An output signal from the subtractor is be filtered by the loop filter, which may effectively perform at least one integration using integrator(s) on the signal output from the subtractor. An output from the loop filter is be fed to the ADC. The ADC generates the output signal y[n], a digital representation of the input signal x[t]. The integrator(s) is/are a source for errors within a typical ΣΔ ADC. In particular, each integrator within the ΣΔ ADC may have an undesirable output swing that causes increased amplifier distortion.
ΣΔ ADCs have been widely used in digital audio and high precision instrumentation systems. More recently, ΣΔ ADCs are finding new application in infrastructure wide-band radio receivers. In the design of ΣΔ ADCs, it is desirable to have small integrator output swing (for a given integrator gain) so the amplifier distortion is smaller and current consumption is lower. Unfortunately, the integrator output swing is determined by coefficients' scaling and supply voltage headroom. When integrators are scaled for smaller swing, their AC gain is also reduced. This results in lager noise contribution from the following stages. In practical design processes, the scaling can be optimized to achieve the best trade-off among the noise, distortion, and power. However, it is desirable to reduce integrator output swing without compromising with noise performance.
Previous efforts to reduce integrator output swing have undesirable side-effects. For example, some techniques introduce a feedfoward path from the input of a first stage integrator in a loop filter to input of the following stage integrator to partially cancel the current generated by the feedback DAC coupled to the same node. The output swing of the front integrator is forced to be smaller by the loop because the net input of the following stage should be close to zero. However, one unobvious byproduct of the feed-forward technique is that the added feedfoward path will change the integrator's signal transfer function (SFT) because of the extra signal path. This effect is usually more severe for out-of-band response and sometimes results in large peaking. Thus, the foregoing design technique is not suitable for designs with stringent STF requirements.